`include "PRV564Config.v"
`include "PRV564Define.v"
//////////////////////////////////////////////////////////////////////////////////////////////////
//  Date    : 2021                                                                              //
//  Author  : Jack.Pan                                                                          //
//  Desc    : Instructions Decode Unit For PRV564 processor                                     //
//  Version : 1.1(fence, fence.i and fence.vma) is changed to DITF, and dispatch buffer is added//
//////////////////////////////////////////////////////////////////////////////////////////////////
module IDU(
//--------------------Global Signals-----------------------
    input wire              IDUi_CLK,
    input wire              IDUi_ARST,
    input wire              IDUi_Flush,            //Flush IDU (Global FLush)
//------------------CSR read interface----------------------
    input wire              IDUi_CSR_tvm,
    input wire              IDUi_CSR_tsr,
    input wire              IDUi_CSR_mpriv,
    input wire [1:0]        IDUi_CSR_mpp,
    input wire [`XLEN-1:0]  IDUi_CSR_data,          //CSR data
    output wire [11:0]      IDUo_CSR_index,         //CSR index
    output wire             IDUo_CSR_en,            //read csr enable
//-----------------Regfile(General Perpose Register) read interface---------------------
    output wire [4:0]       IDUo_GPR_rs1index,
    output wire             IDUo_GPR_rs1en,
    input wire  [`XLEN-1:0] IDUi_GPR_rs1data,
    output wire [4:0]       IDUo_GPR_rs2index,
    output wire             IDUo_GPR_rs2en,
    input wire  [`XLEN-1:0] IDUi_GPR_rs2data,
//-------------------------DITF Check interface----------------------------
    output wire             IDUo_Checken,           //check enable
    output wire [4:0]       IDUo_CheckRs1Index,     //rs1 index for check
    output wire             IDUo_CheckRs1en,        //rs1 index for check is enable
    output wire [4:0]       IDUo_CheckRs2Index,     //rs2 index for check
    output wire             IDUo_CheckRs2en,        //rs2 index for check is enable
    output wire [11:0]      IDUo_CheckCSRIndex,     //csr index for check
    output wire             IDUo_CheckCSRen,        //csr index for check is enable
    input wire              IDUi_DepdcFind,         //A dependencies is found
//--------------------------DITF Write Interface---------------------------
    output reg              IDUo_DITF_write,        //Write enable (add a new entry)
    output wire [7:0]       IDUo_DITF_itag,
    output wire [4:0]       IDUo_DITF_rs1index,
    output wire             IDUo_DITF_rs1en,
    output wire [4:0]       IDUo_DITF_rs2index,
    output wire             IDUo_DITF_rs2en,
    output wire [4:0]       IDUo_DITF_rdindex,
    output wire             IDUo_DITF_rden,
    output wire [11:0]      IDUo_DITF_csrindex,
    output wire             IDUo_DITF_csren,
    output wire             IDUo_DITF_jmp,
    output wire             IDUo_DITF_InsAccessFlt,
    output wire             IDUo_DITF_InsPageFlt,
    output wire             IDUo_DITF_InsAddrMis,
    output wire             IDUo_DITF_illins,
    output wire             IDUo_DITF_mret,
    output wire             IDUo_DITF_sret,
    output wire             IDUo_DITF_fence,
    output wire             IDUo_DITF_fencei,
    output wire             IDUo_DITF_fencevma,
    output wire             IDUo_DITF_ecall,
    output wire             IDUo_DITF_ebreak,
    output wire             IDUo_DITF_system,
    input wire              IDUi_DITF_write_ready,      //DITF is empty now
//-----------FLush & ModifyPermit interface---------
    output reg [`XLEN-1:0]  IDUo_BPC,
    output reg              IDUo_BFlush,                //Flush instruction front
//------------------BTB write----------------------
    output reg [`XLEN-1:0]  IDUo_BTB_wrPC,              //要更新BTB中的源PC
    output reg              IDUo_BTB_wren,              //更新BTB请求
    output reg              IDUo_BTB_wr_predicatebit,   //更新BTB的位，0=不跳 1=跳
    output reg [`XLEN-1:0]  IDUo_BTB_wr_predicatePC,    //更新BTB中对应PC的目标PC
//----------------Pipline input--------------------
    input wire              PIP_IDUi_MSC_valid,         //current instruction is valid
    input wire [`XLEN-1:0]  PIP_IDUi_DATA_instr,        //intruction input (64bit and aligned对齐的)
    input wire [`XLEN-1:0]  PIP_IDUi_INFO_pc,           //current pc
    input wire [`XLEN-1:0]  PIP_IDUi_INFO_predictedPC,
    input wire [1:0]        PIP_IDUi_INFO_priv,
    input wire              PIP_IDUi_MSC_InstPageFlt,
    input wire              PIP_IDUi_MSC_InstAddrMis,
    input wire              PIP_IDUi_MSC_InstAccFlt,
    output reg              PIP_IDUo_FC_ready,
//---------------ALU interface----------------------
    output wire              PIP_ALUi_MSC_valid,
    output wire  [`XLEN-1:0] PIP_ALUi_INFO_pc,
    output wire  [1:0]       PIP_ALUi_INFO_priv,
    output wire  [7:0]       PIP_ALUi_INFO_ITAG,
    output wire  [7:0]       PIP_ALUi_Opcode,
    output wire  [3:0]       PIP_ALUi_OpSize,
    output wire  [1:0]       PIP_ALUi_OPInfo,
    output wire  [`XLEN-1:0] PIP_ALUi_DATA_ds1,
    output wire  [`XLEN-1:0] PIP_ALUi_DATA_ds2,          
    input wire              PIP_ALUo_FC_ready,          //ALU is ready to go
//---------------LSU interface-----------------------
    output wire              PIP_LSUi_MSC_valid,
    output wire  [`XLEN-1:0] PIP_LSUi_INFO_pc,
    output wire  [1:0]       PIP_LSUi_INFO_priv,
    output wire  [7:0]       PIP_LSUi_INFO_ITAG,
    output wire              PIP_LSUi_INFO_unpage,       //unpage mode is on
    output wire  [7:0]       PIP_LSUi_Opcode,
    output wire  [3:0]       PIP_LSUi_OpSize,
    output wire  [1:0]       PIP_LSUi_OPInfo,
    output wire  [`XLEN-1:0] PIP_LSUi_DATA_ds1,
    output wire  [`XLEN-1:0] PIP_LSUi_DATA_ds2,          
    input wire              PIP_LSUo_FC_ready,          //LSU is ready to go
//---------------Math Coprocessor interface----------
    output wire              PIP_Mcopi_MSC_valid,
    output wire  [`XLEN-1:0] PIP_Mcopi_INFO_pc,
    output wire  [1:0]       PIP_Mcopi_INFO_priv,
    output wire  [7:0]       PIP_Mcopi_INFO_ITAG,
    output wire  [7:0]       PIP_Mcopi_Opcode,
    output wire  [3:0]       PIP_Mcopi_OpSize,
    output wire  [1:0]       PIP_Mcopi_OPInfo,
    output wire  [`XLEN-1:0] PIP_Mcopi_DATA_ds1,
    output wire  [`XLEN-1:0] PIP_Mcopi_DATA_ds2,          
    input wire              PIP_Mcopo_FC_ready           //Math coprocessor is ready to go


);
//-----------------------------Instruction and global valid--------------------------------
    reg [31:0]      Instruction;                           //Instruction
    wire            Valid;                                 //Global Valid in IDU
always@(*)begin
    `ifdef DEBUG_FLAG
    case(PIP_IDUi_DATA_instr[6:0])
        7'h6b   : Instruction = 32'hcc051073;         // halt
        7'h7b   : Instruction = 32'hcc151073;         // premappedto csrw 0xcc1,a0
        default : Instruction = PIP_IDUi_DATA_instr[31:0];
    endcase
    `else 
         Instruction = PIP_IDUi_DATA_instr[31:0];
    `endif
end
// 如果上一个派遣出去的指令有冲刷，则当前指令有效位被清零
assign Valid        = (IDUi_Flush | IDUo_BFlush) ? 1'b0 : PIP_IDUi_MSC_valid;
//------------------------------ITAG generate enable---------------------------------------
    reg             ITAG_EN;
//----------------------------dispatch target and dispatch opcode--------------------------
    wire            disp_ALU,       disp_LSU,       disp_Mcop;          //dispatch target
    wire            disp_ALU_ready, disp_LSU_ready, disp_Mcop_ready;    //dispatch ready
    wire [7:0]      disp_opcode;
    wire [1:0]      disp_opinfo;
    wire [3:0]      disp_opsize;                            //dispatch operation size
    wire [`XLEN-1:0]disp_ds1,       disp_ds2;                     //dispatch data source
//-----------------------------Branch address and jump enable------------------------------
    wire [`XLEN-1:0]BP_address;
    wire            BP_jump_pending;                        //一个跳转正在等待，表明当前指令需要进行跳转
    wire            BP_jump_instr;                          //当前指令是一条跳转指令
//-------------------------------Instruction Decode Core-----------------------------------
// ID core将当前指令解码到将要派遣的每个管线上
IDcore              inst_IDcore(
    .CSR_tvm            (IDUi_CSR_tvm),
    .CSR_tsr            (IDUi_CSR_tsr),
    .InstrPriv          (PIP_IDUi_INFO_priv),
    .Instruction        (Instruction),
    .InstructionPC      (PIP_IDUi_INFO_pc),
    .Valid              (Valid),
    .InsAccessFlt       (PIP_IDUi_MSC_InstAccFlt),
    .InsPageFlt         (PIP_IDUi_MSC_InstPageFlt),
    .InsAddrMis         (PIP_IDUi_MSC_InstAddrMis),
    .DITF_FULL          (!IDUi_DITF_write_ready),
    //---------------decode output----------------------
    .rs1_index          (IDUo_CheckRs1Index),
    .rs1_en             (IDUo_CheckRs1en),
    .rs2_index          (IDUo_CheckRs2Index),
    .rs2_en             (IDUo_CheckRs2en),
    .rs1_data           (IDUi_GPR_rs1data),
    .rs2_data           (IDUi_GPR_rs2data),
    .rd_index           (IDUo_DITF_rdindex),
    .rd_en              (IDUo_DITF_rden),
    .csr_index          (IDUo_CheckCSRIndex),
    .csr_en             (IDUo_CheckCSRen),
    .CSR_data           (IDUi_CSR_data),
    .Checken            (IDUo_Checken),
    .DepdcFind          (IDUi_DepdcFind),
    //---------------instruction's information---------------------
    .Info_jmp           (IDUo_DITF_jmp),
    .Info_illins        (IDUo_DITF_illins),
    .Info_mret          (IDUo_DITF_mret),
    .Info_sret          (IDUo_DITF_sret),
    .Info_fence         (IDUo_DITF_fence),
    .Info_fencei        (IDUo_DITF_fencei),
    .Info_fencevma      (IDUo_DITF_fencevma),
    .Info_ecall         (IDUo_DITF_ecall),
    .Info_ebreak        (IDUo_DITF_ebreak),
    .Info_system        (IDUo_DITF_system),
    .BP_address         (BP_address),
    .BP_jmp             (BP_jump_pending),
    .BP_branch          (BP_jump_instr),
    //----------------dispatch dist output-------------------
    .disp_ALU           (disp_ALU),
    .disp_LSU           (disp_LSU),
    .disp_Mcop          (disp_Mcop),
    .disp_opcode        (disp_opcode),
    .disp_opinfo        (disp_opinfo),
    .disp_size          (disp_opsize),
    .disp_ds1           (disp_ds1),
    .disp_ds2           (disp_ds2)
);
//-------------------------------Read CSR and GPR----------------------------
assign IDUo_GPR_rs1index    = IDUo_CheckRs1Index;
assign IDUo_GPR_rs1en       = IDUo_CheckRs1en;
assign IDUo_GPR_rs2index    = IDUo_CheckRs2Index;
assign IDUo_GPR_rs2en       = IDUo_CheckRs2en;
assign IDUo_CSR_index       = IDUo_CheckCSRIndex;
assign IDUo_CSR_en          = IDUo_CheckCSRen;
//-------------------------------TAG generate core---------------------------
TAGgen      ITAG_generate(
    .CLKi               (IDUi_CLK),             //clock input
    .ARSTi              (IDUi_ARST),            //Async reset input
    .ENi                (ITAG_EN),              //随机数产生使能，为1时在下一个cycle生成新的随机数，为0时保持
    .DATAo              (IDUo_DITF_itag)        //随机数输出
);
always@(*) begin
    if(PIP_IDUi_MSC_valid & PIP_IDUo_FC_ready)begin //IDU和前级握手成功，则ITAG指向下一条指令
        ITAG_EN = 1'b1;
    end
    else begin
        ITAG_EN = 1'b0;
    end
end
//-------------------------------BTB write and Flush--------------------------
always@(posedge IDUi_CLK or posedge IDUi_ARST)begin
    if(IDUi_ARST)begin
        IDUo_BTB_wr_predicatebit <= 1'b0;
        IDUo_BTB_wr_predicatePC  <= 64'hx;
        IDUo_BTB_wrPC            <= 64'hx;
        IDUo_BTB_wren            <= 1'b0;
        IDUo_BFlush              <= 1'b0;
        IDUo_BPC                 <= 64'hx;
    end
    else if(disp_ALU&disp_ALU_ready | disp_LSU&disp_LSU_ready | disp_Mcop&disp_Mcop_ready)begin //当前指令被派遣成功
        if(BP_jump_instr)begin
            if(PIP_IDUi_INFO_predictedPC != (PIP_IDUi_INFO_pc + 64'd4))begin            //预测为跳转
                if(BP_jump_pending)begin                                                //当前指令需要跳转
                    if(PIP_IDUi_INFO_predictedPC == BP_address)begin                    //预测跳转预测成功
                        IDUo_BTB_wr_predicatebit <= 1'b1;
                        IDUo_BTB_wr_predicatePC  <= BP_address;
                        IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
                        IDUo_BTB_wren            <= 1'b1;
                        IDUo_BFlush              <= 1'b0;
                        IDUo_BPC                 <= 64'hx;
                    end
                    else begin              //预测失败，实际跳转地址和真实地址不一致
                        IDUo_BTB_wr_predicatebit <= 1'b1;
                        IDUo_BTB_wr_predicatePC  <= BP_address;
                        IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
                        IDUo_BTB_wren            <= 1'b1;
                        IDUo_BFlush              <= 1'b1;
                        IDUo_BPC                 <= BP_address;
                    end
                end
                else begin                                          //预测跳转失败，冲刷流水线
                    IDUo_BTB_wr_predicatebit <= 1'b0;
                    IDUo_BTB_wr_predicatePC  <= BP_address;
                    IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
                    IDUo_BTB_wren            <= 1'b1;
                    IDUo_BFlush              <= 1'b1;
                    IDUo_BPC                 <= (PIP_IDUi_INFO_pc + 64'd4);
                end
            end
            else begin                                          //预测为不跳转
                if(!BP_jump_pending)begin                       //预测为不跳转成功
                    IDUo_BTB_wr_predicatebit <= 1'b0;
                    IDUo_BTB_wr_predicatePC  <= BP_address;
                    IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
                    IDUo_BTB_wren            <= 1'b1;
                    IDUo_BFlush              <= 1'b0;
                    IDUo_BPC                 <= 64'hx;
                end
                else begin      //预测不跳转失败，冲刷流水线
                    IDUo_BTB_wr_predicatebit <= 1'b1;
                    IDUo_BTB_wr_predicatePC  <= BP_address;
                    IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
                    IDUo_BTB_wren            <= 1'b1;
                    IDUo_BFlush              <= 1'b1;
                    IDUo_BPC                 <= BP_address;
                end
            end
        end
        else begin                  //当前指令不是跳转指令
            if(PIP_IDUi_INFO_predictedPC != (PIP_IDUi_INFO_pc + 64'd4))begin    //当前错误预测了跳转
                IDUo_BTB_wr_predicatebit <= 1'b0;
                IDUo_BTB_wr_predicatePC  <= BP_address;
                IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
                IDUo_BTB_wren            <= 1'b1;
                IDUo_BFlush              <= 1'b1;
                IDUo_BPC                 <= (PIP_IDUi_INFO_pc + 64'd4);
            end
            else begin              //没有预测跳转，不写BTB表项
                IDUo_BTB_wr_predicatebit <= 1'b0;
                IDUo_BTB_wr_predicatePC  <= BP_address;
                IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
                IDUo_BTB_wren            <= 1'b0;
                IDUo_BFlush              <= 1'b0;
                IDUo_BPC                 <= 64'hx;
            end
        end
    end
    else begin      //当前无派遣
        IDUo_BTB_wr_predicatebit <= 1'b0;
        IDUo_BTB_wr_predicatePC  <= BP_address;
        IDUo_BTB_wrPC            <= PIP_IDUi_INFO_pc;
        IDUo_BTB_wren            <= 1'b0;
        IDUo_BFlush              <= 1'b0;
        IDUo_BPC                 <= 64'hx;
    end
end
//-------------------------------dispatch buffers-----------------------------
DispBuffer                  ALU_DispBuffer(
    .DBi_CLK                    (IDUi_CLK),
    .DBi_ARST                   (IDUi_ARST),
    .DBi_Flush                  (IDUi_Flush),
//---------------输入------------------
    .DBi_MSC_valid              (disp_ALU),
    .DBi_INFO_pc                (PIP_IDUi_INFO_pc),
    .DBi_INFO_priv              (PIP_IDUi_INFO_priv),
    .DBi_INFO_ITAG              (IDUo_DITF_itag),
    .DBi_INFO_unpage            (1'b0),
    .DBi_Opcode                 (disp_opcode),
    .DBi_OpSize                 (disp_opsize),
    .DBi_OPInfo                 (disp_opinfo),
    .DBi_DATA_ds1               (disp_ds1),
    .DBi_DATA_ds2               (disp_ds2),
    .DBo_ready                  (disp_ALU_ready),
//------------Buffer输出---------------
    .DBo_MSC_valid              (PIP_ALUi_MSC_valid),
    .DBo_INFO_pc                (PIP_ALUi_INFO_pc),
    .DBo_INFO_priv              (PIP_ALUi_INFO_priv),
    .DBo_INFO_ITAG              (PIP_ALUi_INFO_ITAG),
    .DBo_INFO_unpage            (),                          //not use
    .DBo_Opcode                 (PIP_ALUi_Opcode),
    .DBo_OpSize                 (PIP_ALUi_OpSize),
    .DBo_OPInfo                 (PIP_ALUi_OPInfo),
    .DBo_DATA_ds1               (PIP_ALUi_DATA_ds1),
    .DBo_DATA_ds2               (PIP_ALUi_DATA_ds2),
    .DBi_FC_ready               (PIP_ALUo_FC_ready)
);

DispBuffer                  LSU_DispBuffer(
    .DBi_CLK                    (IDUi_CLK),
    .DBi_ARST                   (IDUi_ARST),
    .DBi_Flush                  (IDUi_Flush),
//---------------输入------------------
    .DBi_MSC_valid              (disp_LSU),
    .DBi_INFO_pc                (PIP_IDUi_INFO_pc),
    .DBi_INFO_priv              (PIP_IDUi_INFO_priv),
    .DBi_INFO_ITAG              (IDUo_DITF_itag),
    .DBi_INFO_unpage            ((PIP_IDUi_INFO_priv == `Machine) & IDUi_CSR_mpriv & (IDUi_CSR_mpp==`Machine)),
    .DBi_Opcode                 (disp_opcode),
    .DBi_OpSize                 (disp_opsize),
    .DBi_OPInfo                 (disp_opinfo),
    .DBi_DATA_ds1               (disp_ds1),
    .DBi_DATA_ds2               (disp_ds2),
    .DBo_ready                  (disp_LSU_ready),
//------------Buffer输出---------------
    .DBo_MSC_valid              (PIP_LSUi_MSC_valid),
    .DBo_INFO_pc                (PIP_LSUi_INFO_pc),
    .DBo_INFO_priv              (PIP_LSUi_INFO_priv),
    .DBo_INFO_ITAG              (PIP_LSUi_INFO_ITAG),
    .DBo_INFO_unpage            (PIP_LSUi_INFO_unpage),
    .DBo_Opcode                 (PIP_LSUi_Opcode),
    .DBo_OpSize                 (PIP_LSUi_OpSize),
    .DBo_OPInfo                 (PIP_LSUi_OPInfo),
    .DBo_DATA_ds1               (PIP_LSUi_DATA_ds1),
    .DBo_DATA_ds2               (PIP_LSUi_DATA_ds2),
    .DBi_FC_ready               (PIP_LSUo_FC_ready)
);
DispBuffer                  Mcop_DispBuffer(
    .DBi_CLK                    (IDUi_CLK),
    .DBi_ARST                   (IDUi_ARST),
    .DBi_Flush                  (IDUi_Flush),
//---------------输入------------------
    .DBi_MSC_valid              (disp_Mcop),
    .DBi_INFO_pc                (PIP_IDUi_INFO_pc),
    .DBi_INFO_priv              (PIP_IDUi_INFO_priv),
    .DBi_INFO_ITAG              (IDUo_DITF_itag),
    .DBi_INFO_unpage            (1'b0),
    .DBi_Opcode                 (disp_opcode),
    .DBi_OpSize                 (disp_opsize),
    .DBi_OPInfo                 (disp_opinfo),
    .DBi_DATA_ds1               (disp_ds1),
    .DBi_DATA_ds2               (disp_ds2),
    .DBo_ready                  (disp_Mcop_ready),
//------------Buffer输出---------------
    .DBo_MSC_valid              (PIP_Mcopi_MSC_valid),
    .DBo_INFO_pc                (PIP_Mcopi_INFO_pc),
    .DBo_INFO_priv              (PIP_Mcopi_INFO_priv),
    .DBo_INFO_ITAG              (PIP_Mcopi_INFO_ITAG),
    .DBo_INFO_unpage            (),                          //not use
    .DBo_Opcode                 (PIP_Mcopi_Opcode),
    .DBo_OpSize                 (PIP_Mcopi_OpSize),
    .DBo_OPInfo                 (PIP_Mcopi_OPInfo),
    .DBo_DATA_ds1               (PIP_Mcopi_DATA_ds1),
    .DBo_DATA_ds2               (PIP_Mcopi_DATA_ds2),
    .DBi_FC_ready               (PIP_Mcopo_FC_ready)
);

//-----------------------------DITF write & ready--------------------------------
assign IDUo_DITF_InsAddrMis     = PIP_IDUi_MSC_InstAddrMis;
assign IDUo_DITF_InsAccessFlt   = PIP_IDUi_MSC_InstAccFlt;
assign IDUo_DITF_InsPageFlt     = PIP_IDUi_MSC_InstPageFlt;
assign IDUo_DITF_rs1index       = IDUo_CheckRs1Index;
assign IDUo_DITF_rs1en          = IDUo_CheckRs1en;
assign IDUo_DITF_rs2index       = IDUo_CheckRs2Index;
assign IDUo_DITF_rs2en          = IDUo_CheckRs2en;
assign IDUo_DITF_csrindex       = IDUo_CheckCSRIndex;
assign IDUo_DITF_csren          = IDUo_CheckCSRen;
always@(*)begin
    if(PIP_IDUi_MSC_valid)begin
        if(disp_ALU)begin
            PIP_IDUo_FC_ready = disp_ALU_ready ? 1'b1 : 1'b0;      //if valid output = ready, 即valid，ready=0，0和1，1，表示派遣成功，否则不成功 
            IDUo_DITF_write   = disp_ALU_ready ? 1'b1 : 1'b0;      //if valid 和 ready 均为1或者均为0，表示后级有指令且准备好或无指令，可以派遣
        end
        else if(disp_LSU)begin
            PIP_IDUo_FC_ready = disp_LSU_ready ? 1'b1 : 1'b0;
            IDUo_DITF_write   = disp_LSU_ready ? 1'b1 : 1'b0;      
        end
        else if(disp_Mcop)begin
            PIP_IDUo_FC_ready = disp_Mcop_ready ? 1'b1 : 1'b0;
            IDUo_DITF_write   = disp_Mcop_ready ? 1'b1 : 1'b0;      
        end
        else begin
            PIP_IDUo_FC_ready = (IDUi_Flush | IDUo_BFlush) ? 1'b1 : 1'b0;  //if no dispatch, the instruction is waiting
            IDUo_DITF_write   = 1'b0;
        end
    end
    else begin
        PIP_IDUo_FC_ready = 1'b0;
        IDUo_DITF_write   = 1'b0;
    end
end

endmodule
